The Core 2's FSB, RAM and Bandwidth Explained

The Core 2's FSB, RAM and Bandwidth Explained - Icrontic.com

The Core 2's FSB, RAM and Bandwidth Explained

Make sense of the numbers

by Robert Hallock published Jan 20, 2008

Filed under: tweaks, processors, overclocking, motherboards, memory

Today, Icrontic serves up a crash-course in the mysterious relationship of the Core 2 front side bus, RAM and bandwidth. The nature of the Core 2's design may be baffling, particularly to users exiting the era of synchronized Athlon XP buses, and we intend to cut through the haze and serve it straight just as we like to. Before we begin, however, there is a bit of background information that we will establish so we can quickly dispense with the rest of the juicy morsels.

A crash course in Intel's bus architecture

Since the days of the Pentium 4, Intel has employed a bus technology known as Assisted Gunning Transceiver Logic+ (PDF), or AGTL+. AGTL+, and other logics like it, specifies how communication across your front side bus is to occur.